1. Field of the Invention
The present invention relates to a semiconductor memory device (such as DRAM and SRAM) comprising a memory cell array potion and a peripheral circuit portion.
2. Description of the Related Art
As higher-density and larger-scale integration is pursued in an LSI memory, the structure thereof has tended to extend in three dimensions. Accordingly, the height of its memory cell array portion has increased, resulting in a greater difference in level between the memory cell array portion and the peripheral circuit portion including a decoder, a sense amplifier, and an input-output buffer. The difference in height leads to an uneven surface, which may cause problems in the fine processing of wires installed over the memory cell array portion and peripheral circuit portion, such as the breaking of a wire or the increase in resistance value due to the non-uniform width of a wire.
In order to reduce the difference in level mentioned above, the prior art has adopted a method in which the surface of a predetermined region of the substrate is previously removed to form a hollow portion for the memory cell array portion (e.g. Japanese Unexamined Patent Publication Nos. SHO 63-266866(1988) and SHO 63-132471(1988)). The conventional method will be described below.
First, as shown in FIG. 2A, the region of the substrate for the peripheral circuit portion is masked with a layer of Si.sub.3 N.sub.4, so as to exclusively oxidize the region of the substrate for the memory cell array portion by thermal oxidization.
In the drawing, the substrate 1 of Si and a layer 2 of SiO.sub.2 are shown. The SiO.sub.2 layer 2 is subsequently removed in a HF solution, so that a hollow portion for the memory cell array portion can be formed in the substrate (FIG. 2B). After the formation of a memory cell array on the hollow portion and transistors in the peripheral circuit portion, the memory cell array portion and the peripheral circuit portion are coated with a BPSG layer which is then heat-treated to provide an ever surface (FIG. 2C). In FIG. 2C, the difference in level d.sub.2 before the wiring step and a layer 3 of BPSG are shown. Thereafter, the metal wiring 4 is provided on the BPSG layer as shown in FIG. 2D.
The method, however, is disadvantageous in that the substrate is damaged through the formation of the hollow portion. That is, the local growth of the SiO.sub.2 layer 2 for the hollow portion causes great stress in the Si substrate during the oxidization treatment. As a result, there were some cases where the operation as a memory device was adversely affected. Moreover, a on period of treatment is required to obtain a sufficiently deep hollow portion, which is not appropriate for mass fabrication.